Computer Architecture Letters - IEEE - News Items
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Exploiting Internal Parallelism of Flash-based SSDs
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
For the last few years, the major driving force behind the rapid performance improvement of SSDs has been the increment of parallel bus channels between a flash controller and flash memory ... (Read More)
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Intra-Socket and Inter-Socket Communication in Multi-core Systems
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
The increasing computational and communication demands of the scientific and industrial communities require a clear understanding of the performance trade-offs involved in multi-core computing ... (Read More)
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A Case for Alternative Nested Paging Models for Virtualized Systems
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Address translation often emerges as a critical performance bottleneck for virtualized systems and has recently been the impetus for hardware paging mechanisms. These mechanisms apply similar ... (Read More)
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Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
While Moore’s law scaling continues to double transistor density every technology generation, supply voltage reduction has essentially stopped, increasing both power density and total energy ... (Read More)
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SMT-Directory: Efficient Load-Load Ordering for SMT
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any thread appear to occur in program order to all other threads. Out-of-order execution can violate ... (Read More)
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A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by the large ... (Read More)
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Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Power is of paramount importance in modern computer system design. In particular, the cache interconnect in future CMP designs is projected to consume up to half of the system power for cache ... (Read More)
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Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Rate-based metrics such as floating point operations per second, instructions per cycle and so forth are commonly used to measure computer performance. In addition to the average or mean ... (Read More)
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A Phase Change Memory as a Secure Main Memory
Tuesday, June 08, 2010 - 04:20 AM - 1 month, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Phase change memory (PCM) technology appears as more scalable than DRAM technology. As PCM exhibits access time slightly longer but in the same range as DRAMs, several recent studies have proposed ... (Read More)
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Tuesday, January 12, 2010 - 04:20 AM - 6 months, 2 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Monday, January 11, 2010 - 04:20 AM - 6 months, 2 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Sunday, January 10, 2010 - 04:19 AM - 6 months, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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Saturday, January 09, 2010 - 04:20 AM - 6 months, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE |
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PRR-PRR Dynamic Relocation
Friday, January 08, 2010 - 04:20 AM - 6 months, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Partial bitstream relocation (PBR) on FPGAs has been gaining attention in recent years as a potentially promising technique to scale parallelism of accelerator architectures at run time, enhance ... (Read More)
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Power Management of Datacenter Workloads Using Per-Core Power Gating
Friday, January 08, 2010 - 04:20 AM - 6 months, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, a.k.a. P-states) to achieve energy ... (Read More)
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A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors
Friday, January 08, 2010 - 04:20 AM - 6 months, 3 weeks ago - Computer Science - Computer Architecture Letters - IEEE
Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures. Isolating each core with its own frequency and voltage ... (Read More)
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